The present invention relates to a method of estimating a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit.
To reduce the power dissipated by a semiconductor integrated circuit or to increase the operating speed thereof, a supply voltage to be applied to the circuit sometimes needs to be changed selectively. This is because if the supply voltage is changed, then a signal will be propagated through the circuit at a different rate and eventually the power consumed by the circuit will be changeable also. However, once the supply voltage is replaced with a newly selected one, the circuit will cause a different amount of time delay. Thus, it is necessary for the designer of the circuit to know the time delay that will be estimatingly caused by the circuit upon the application of the selected voltage. And then the designer needs to make sure whether or not the circuit still can operate normally even if the circuit should cause the time delay in that estimated amount.
Generally speaking, while a circuit is being laid out, a time delay caused by each of the cells for the circuit can be represented as a function of the transition time of a signal wave input to the cell and the capacitance of a load driven by the cell. The function may be represented by either a table indexed by transition time and load capacitance or an equation that also uses transition time and load capacitance as arguments. Although each of these methods has its own advantages and disadvantages, the former table method is usually preferred because the time delay can be represented much more freely than the other. It should be noted that tables such as those illustrated in FIG. 3 will be herein called xe2x80x9cdelay tablesxe2x80x9d.
In representing a circuit""s time delays as a delay table, if there are two or more supply voltages applicable to the circuit, then the same number of delay tables should be prepared. That is to say, one delay table needs to be provided for each supply voltage. Each of those delay tables can be compiled from time delays, which were measured as representative values for a combination of transition times and load capacitances through circuit simulations. As used herein, the combination of transition times and load capacitances, from which a delay table is compiled, will be called xe2x80x9cdelay table indicesxe2x80x9d. Accordingly, to newly compile a delay table, the time delays caused by each cell need to be measured by performing simulations on the circuit. Thus, it takes a great deal of man-hour to prepare a delay table for each and every supply voltage to be applied.
A technique of eliminating this problem is proposed in Japanese Laid-Open Publication No. 11-3366, for example. According to the technique, a reference time delay is calculated using a combination of circuit operation conditions, including predefined supply voltage, process variation and temperature, as a reference combination. Next, a coefficient table is prepared. On this table, various time delay coefficients, corresponding to respective combinations of circuit operation conditions (which are determined by multiple combinations of variable elements prepared for the reference time delay), are stored. And by multiplying the reference time delay by a time delay coefficient associated with a given combination of circuit operation conditions, a time delay, which will be caused under the given conditions, is obtained for each cell. In this manner, the technique makes it possible to obtain an estimated time delay associated with a target supply voltage without compiling any new delay table.
However, the present inventors found out based on results of experiments that the variation of time delay against supply voltage is actually not uniform but changeable among respective cells (i.e., depending on the type of a cell in question). For that reason, according to the technique disclosed in the above-identified publication, the time delay estimated almost always contains a certain amount of error, because the same coefficient is applied to each and every cell irrespective of its type. As a result, the time delay associated with the given supply voltage cannot be estimated accurately enough by such a method. And we found that the variation of time delay against supply voltage is changeable among cells because the threshold voltages of the cells are different from each other.
Hereinafter, it will be described with reference to FIGS. 19 and 20 specifically how the difference in threshold voltage of cells affects the time delays of the cells. In FIGS. 19 and 20, IN denotes the waveform of a signal input to a given cell, OUT denotes the waveform of the output signal of the cell, and Vth101 denotes a threshold voltage used as a reference voltage in estimating the time delay. It should be noted that the threshold voltage Vth101 is defined for convenience sake only and is different from the threshold voltage specific to an individual cell. As used herein, the xe2x80x9cthreshold volt agexe2x80x9d of a cell refers to a voltage at which a signal level transition starts to be propagated to the next stage. Accordingly, when cells designed are actually implemented, the threshold voltage is variable among those cells. Also, even in a single cell, if the cell has two or more input terminals, then the threshold voltage is also variable among the input terminals. And the threshold voltage is changeable as well depending on the voltage of signal input. In the known methods, however, the threshold voltage is supposed to be constant due to various constraints involved with a CAD tool. As shown in FIG. 19, the time delay T101 of a cell is herein defined as an interval between the instant the level of the input signal wave IN reaches the threshold voltage Vth101 and the instant the level of the output signal waveform OUT reaches the threshold voltage Vth101. Suppose a signal wave IN11 has been presented to a predetermined input terminal. Then, as shown in FIG. 20, the actual threshold voltage at the input terminal will be Vth112 and Vth113 for supply voltages V1 and V2, respectively. It should be noted that the voltages Vth2 and Vth113 are herein normalized with the supply voltages V1 and V2, respectively. In this case, if the supply voltage has changed from V1 into V, then the threshold voltage will also change from Vth112 into vth113 and the time delay T101 will also change by the lag T114. The time lag T114 only reflects the variation in threshold voltage. Accordingly, the time delay T101 is actually further variable depending on a variation in drivability as well.
As can be seen, the time lag T114 is variable among individual cells or among respective input terminals in a cell. In spite of this fact, if the same combination of circuit operation conditions is applicable, the same coefficient is automatically used for each and every cell according to the known delay estimating method. Thus, such a technique cannot take a variation in delay, resulting from the time lag T114, into account.
FIG. 21 illustrates respective ratios of time delays, resulting from various supply voltages applied to five types of cells, to a reference time delay associated with a reference supply voltage of 2.5 V. As shown in FIG. 21, the supply voltage applied was changed between 1.8 V and 2.7 V at a scale of 0.1 V and the time delays were estimated through circuit simulations. In this case, the cells used were inverter, five-input NAND gate, five-input NOR gate, buffer, five-input AND gate and five-input OR gate. The ratios were also obtained for the rise and fall of the output signal waveform of each cell. As can be seen from FIG. 21, the time delay obviously changes depending on the type of a cell.
FIG. 22 illustrates respective ratios of time delays, caused by an inverter at ten different supply voltages, to a reference time delay associated with a reference supply voltage of 2.5 V. In the example illustrated in FIG. 22, the inverter was operated under nine different combinations of transition times of input signal wave and load capacitances. As shown in FIG. 22, the supply voltage applied was also changed between 1.8 V and 2.7 V at a scale of 0.1 V and the time delays were estimated through circuit simulations. As can be easily seen from FIG. 22, the time delay obviously changes depending on the combination of transition time of the input signal wave and load capacitance.
It is therefore an object of the present invention to provide a method of accurately estimating a time delay that will be caused by a given cell for a target supply voltage by taking the cell-by-cell variation in time delay against supply voltages.
To achieve this object, according to the present invention, a time delay to be caused by a predetermined cell (i.e., representative cell) is represented in advance as a function of supply voltage. In addition, at least two delay tables, corresponding to mutually different supply voltages, are also prepared for a target cell for which a time delay should eventually be estimated. Then, a function is derived exclusively for the target cell by modifying the former function using the delay tables. And by using the newly derived function, the time delay caused by the target cell at a target supply voltage is estimated.
Also, according to the present invention, a correction value is added to a time delay, which has been obtained simply by multiplying the reference time delay by the same coefficient as in the known methods, so that the delay can be estimated accurately enough for a specific type of cell.
Furthermore, according to the present invention, even if a single delay table has been prepared for just one supply voltage, an interpolation function, representing a relation between the time delays caused by the target cell and the supply voltages, is derived. And in accordance with the interpolation function, the time delays, which will be caused by each of multiple instances, are estimated for the supply voltages applied to the instance by reference to the transition times of a signal input to the instance and the output load capacitances.
Specifically, an inventive delay estimating method is applicable to estimation of a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit. The method includes the steps of: a) deriving an approximation function; b) deriving an interpolation function; c) compiling a third delay table; and d) estimating the time delay caused by a target cell. First, in the step a), time delays, which correspond to various supply voltages to be applied to a representative one of the cells and which have been obtained in advance through circuit simulations or actual measurement, are read out. Then, a relation between the time delays and the supply voltages applied to the representative cell is derived as the approximation function. Next, in the step b), first and second delay tables, which were prepared in advance for first and second ones of the supply voltages, are consulted as to a target one of the cells, for which a time delay associated with a target one of the supply voltages should be obtained. Then, a relation between the time delays of the target cell and the supply voltages is represented as the interpolation function by reference to the time delays described on the first and second delay tables and the approximation function. Subsequently, in the step c), the third delay table is compiled for a combination of transition times of an input signal wave and output load capacitances in accordance with the interpolation function in a situation where the target supply voltage is applied to the target cell. Finally, in the step d), the time delay to be caused by the target cell at the target sup ply voltage is estimated by searching the third delay table for one of the transition times and one of the output load capacitances that are associated with the target cell.
Another inventive delay estimating method is also applicable to estimation of a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit. The method includes the steps of: a) deriving an approximation function; b) compiling third and fourth delay tables from first and second tables read out; c) deriving an interpolation function; d) compiling a fifth delay table; and e) estimating the time delay caused by a target cell. First, in the step a), time delays, which correspond to various supply voltages to be applied to a representative one of the cells and which have been obtained in advance through circuit simulations or actual measurement, are read out. Then, a relation between the time delays and the supply voltages applied to the representative cell is derived as the approximation function. In the step b), the first table describes time delays, caused by a target one of the cells, for which a time delay associated with a target one of the supply voltages should be obtained, using a first combination of transition times of an input signal wave and load capacitances in a situation where a first one of the supply voltages is applied to the target cell. The second table describes the time delays, caused by the target cell, using a second combination of transition times of the input signal wave and load capacitances in a situation where a second one of the supply voltages is applied to the target cell. The third and fourth tables describe the time delays caused by the target cell using a third combination, obtained by combining the first and second combinations together, in situations where the first and second supply voltages are applied to the target cell, respectively. Then, in the step c), the interpolation function is derived as a relation between the time delays caused by the target cell and the supply voltages by reference to the time delays described on the third and fourth delay tables and the approximation function. Subsequently, in the step d), the fifth delay table is compiled for the third combination of transition times of the input signal wave and output load capacitances in accordance with the interpolation function in a situation where the target supply voltage is applied to the target cell. Finally, in the step e), the time delay to be caused by the target cell at the target supply voltage is estimated by searching the fifth delay table for one of the transition times and one of the output load capacitances that are associated with the target cell.
In one embodiment of the present invention, the third combination may be obtained in the step b) by deriving a logical sum of the first and second combinations.
In an alternative embodiment, the third combination may also be obtained in the step b) by performing linear interpolation on the first and second combinations.
Still another inventive delay estimating method is also applicable to estimation of a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit. The method includes the steps of: a) deriving an approximation function; b) calculating first and second time delays; c) deriving an interpolation function; and d) estimating the time delay caused by a target cell. First, in the step a), time delays, which correspond to various supply voltages to be applied to a representative one of the cells and which have been obtained in advance through circuit simulations or actual measurement, are read out. Then, a relation between the time delays and the supply voltages applied to the representative cell is derived as the approximation function. Next, in the step b), the first and second time delays that will be caused by a target one of the cells, for which a time delay associated with a target one of the supply voltages should be obtained, are calculated in situations where first and second ones of the supply voltages are applied to the target cell, respectively. Subsequently, in the step c), the interpolation function is derived as a relation between the time delays of the target cell and the supply voltages by reference to the approximation function and the first and second time delays. Finally, in the step d), the time delay to be caused by the target cell at the target supply voltage is estimated in accordance with the interpolation function.
In one embodiment of the present invention, mutually different approximation functions may be derived in the step of deriving the approximation function for rise and fall of an output signal of the representative cell.
In another embodiment of the present invention, the interpolation function g(Vdd) may be defined in the step of deriving the interpolation function as:
g(Vdd)=f(Vdd)*A+B
where f(Vdd) is the approximation function and A and B are first and second constants, respectively. The first and second constants A and B may be set to such values as making the interpolation function g(Vdd) equal to a time delay T1 at the first supply voltage and equal to a time delay T2 at the second supply voltage, respectively.
In still another embodiment, if delay tables corresponding to at least three of the supply voltages have been prepared, the inventive method may further include the step of selecting two of the tables, corresponding to two of the voltages that are closest to the target voltage, as the tables for use in the step of deriving the interpolation function.
Yet another inventive delay estimating method is also applicable to estimation of a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit. The method includes the steps of: a) measuring first, second, third and fourth threshold voltages of a representative one of the cells; b) calculating first and second time delays; and c) estimating a time delay caused by a target cell. In the step a), the first threshold voltage has been normalized by a first supply voltage applied to the representative cell at an input terminal thereof. The second threshold voltage has been normalized by a second sup ply voltage applied to the representative cell at the input terminal thereof. The third threshold voltage has been normalized by the first supply voltage applied to a target one of the cells, for which a time delay associated with a target one of the supply voltages should be obtained, at an input terminal thereof. And the fourth threshold voltage has been normalized by the second supply voltage applied to the target cell at the input terminal thereof. In the step b), first, a ratio of a time delay caused by the representative cell at the second supply voltage to a time delay caused by the representative cell at the first supply voltage is calculated. Next, a first time delay, corresponding to a given transition time of an input signal wave and a given load capacitance, is derived from a delay table describing time delays to be caused by the target cell where the first supply voltage is applied to the target cell. Then, a product of a difference between the first and third threshold voltages and the transition time of the input signal wave is added to the first time delay to obtain a sum. And the sum is multiplied by the ratio, thereby deriving a second time delay. In the step c), the time delay, caused by the target cell at the second supply voltage, is estimated as a third time delay by adding a product of a difference between the second and fourth threshold voltages and the transition time of the input signal wave to the second time delay.
Yet another inventive delay estimating method is also applicable to estimation of a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit. The method includes the steps of: a) deriving an approximation function; b) obtaining delay data; c) deriving an interpolation function; and d) estimating a time delay. First, in the step a), time delays, which correspond to various supply voltages to be applied to a representative one of the cells and which have been obtained in advance through circuit simulations or actual measurement, are read out. Then, a relation between the time delays and the supply voltages applied to the representative cell is derived as the approximation function. Next, in the step b), delay data of respective instances, which make up the circuit, for the first supply voltage is obtained by reading out delay tables for the first supply voltage and calculating respective time delays, which will be caused by the instances, using the delay tables. Subsequently, in the step c), an interpolation function is derived for each said instance by reading out the approximation function and adding a constant, which is defined by reference to the delay data of the instances for the first supply voltage, to the approximation function. Finally, in the step d), data, representing the interpolation functions of the instances and the supply voltages applied to the instances, are read out to estimate a time delay caused by each said instance in accordance with associated one of the interpolation functions in a situation where the supply voltage as represented by the data is applied to the instance.
In one embodiment of the present invention, the cells are classified in the step a) into multiple groups according to circuit structures of the cells. The representative cell is selected from each of the groups and the approximation function is derived for each said representative cell. And the method further includes the step of selecting one of the approximation functions of the respective representative cells, which is associated with one of the groups where the instances causing the time delay calculated in the step b) be long, and reading out the approximation function in the step c).
According to the present invention, an interpolation function, representing a relation between time delays caused by each target cell and supply voltages applied thereto, is derived from an approximation function representing a relation between time delays caused by a representative cell and supply voltages applied thereto. And in accordance with the interpolation function, a time delay, which will be caused by the target cell when a target supply voltage is applied thereto, is estimated. In this manner, a time delay that will be caused by each target cell can be estimated with the threshold voltage of the cell taken into account. As a result, the time delay caused by the target cell can always be estimated accurately irrespective of the supply voltage value.
In addition, according to the present invention, a time delay caused by a representative cell at an arbitrary supply voltage is modified using a correction value that has been determined with the threshold voltage of a target cell taken in to account. As a result, the time delay caused by the target cell can always be estimated accurately irrespective of the supply voltage value.
Furthermore, according to the present invention, even if only a single delay table has been prepared for just one supply voltage, interpolation functions, representing a relation between time delays and supply voltages, are derived for respective instances. And in accordance with the interpolation function for each of these instances, a time delay caused by the instance at a target supply voltage is estimated. Accordingly, the time delay caused by each instance can be estimated accurately at any supply voltage.